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ZL50111 PRODUCT PROFILE

1024 Channel (32 T1/E1, 2 T3/E3) CESoP Processor with triple Ethernet interface

Product Status: Production

The ZL50111 is a highly functional TDM to Packet bridging device that provides structured and unstructured circuit emulation services (CES) for T1/E1 streams across a packet network based on Ethernet technology. The ZL50111 is capable of assembling user-defined packets of TDM traffic from the TDM access interface and transmitting them from the Ethernet interfaces using a variety of protocols such as Ethernet VLAN's, IP (both versions 4 and 6) and MPLS. The device also supports four different classes of service on packet egress, allowing priority treatment of TDM-based traffic. The circuit emulation features in the ZL50111 comply with the relevant standards currently being developed within the IETF's PWE3 working group. The ZL50111 incorporates a range of powerful clock recovery mechanisms and sufficient on-chip memory that external memory is not required in most applications. This reduces system costs and simplifies the design.

Simplified Block Diagram


Features & Benefits

  • 1024 bi-directional 64 kbps channels in structured, synchronous CES
  • 32 T1/E1 or 2 T3/E3 unstructured, asynchronous CES, with integral per stream clock recovery
  • Interface either directly to LIU, via a framer, or via a TDM backplane
  • Dual reference Stratum 3, 4 and 4E PLL for synchronous operation
  • 3 x 100 Mbps MII or Dual Redundant 1000 Mbps GMII/PCS(TBI) Ethernet Interfaces
  • Flexible 32 bit host CPU interface (Motorola PowerQUICCTM II compatible)
  • On-chip packet memory for self-contained operation, with buffer depths of over 16 ms
  • Flexible, multi-protocol packet encapsulation
  • Packet sequencing to allow lost packet detection
  • Four classes of service with programmable priority mechanisms (WFQ and SP)
  • Classification of incoming packets at layers 2, 3, 4, and 5

Downloads, Firmware and Drivers

Typical Applications

  • Leased Line support over packet network
  • Multi-Tenant Unit access concentration
  • Packet switched backplane applications
  • TDM backplane extension / expansion

Related Functions

Product Packaging & Availability

Part
Number
Package
Type
Pin Count
Lead-Free
Option
Shipping
Option(s)
Lead
Time(wks)
Status
ZL50111GAGPBGA552Trays. Bake & Drypack6-8 weeksProduction
ZL50111GAG2PBGA552Pb-free-Tin/Silver/CopperTrays. Bake & Drypack10-12 weeksProduction

Packaging Information

Technical Support

Related Products
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ZL50117   128 Channel (4 T1/E1, 1 T3/E3/STS-1) CESoP Processor with single Ethernet interface
ZL50116   64 Channel (2 T1/E1) CESoP Processor with single Ethernet interface
ZL50115   32 Channel (1 T1/E1) CESoP Processor with single Ethernet interface
ZL50114   128 Channel (4 T1/E1) CESoP Processor with Dual Ethernet Interface
ZL50110   256 Channel (8 T1/E1) CESoP Processor with Dual Ethernet Interface