Circuit emulation services over packet (CESoP) are accelerating the deployment of metro Ethernet/IP networks by allowing equipment to transport high volumes of TDM services with carrier grade quality.

Zarlink's CESoP processors can be used at every point in the system where equipment bridges the TDM circuit-switched infrastructure to the Ethernet/IP network. As shown, the ZL50111 is easily implemented in a CES card that supports up to 32 T1, 32 E1, 8 J2, 2 T3 or 2 E3 streams on one side, and an Ethernet/IP backplane on the other side. In this system, the ZL50111 receives data from the TDM stream, assembles user-defined packets of TDM traffic, and transmits them over packet-switched networks using RTP, UDP, Ethernet VLANs, IPv4, IPv6, MPLS or user defined protocols. The packet engine is programmable and can support changing requirements.

The ZL50111 ensures high QoS, able to support four classes of service on packet egress for priority treatment of time-sensitive traffic. When packets are received from the Ethernet network, they are parsed to determine the egress destination, queued based on sequence number, and lost packets are filled in to maintain timing integrity.

In further support of high QoS, on-chip per-stream Digitally Controlled Oscillator (DCO) ensures precise synchronization across the Ethernet network. Patent-pending software technology supports adaptive or differential timing so the best scheme can be used for a given application.

For added fl exibility, the ZL50111 can be confi gured to act as the master or slave timing source using the imbedded Stratum 3/4/4E DPLL.

In addition to the embedded timing solution, the ZL50111 is equipped with on-board memory that compensates for up to 16ms of packet delay variations (PDV) in the network with external support for up to 128 ms.

Zarlink's single-chip approach eliminates external circuitry, enabling a system-level solution with at least 80% saving in board area compared to equivalent discrete designs using communication processors.